At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267 operates at 900 MFLOPS performance whether operating on fixed or floating point data 300 MMACS sustained perfor.

with its dualported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an in.

The ADSP-21267 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices' Super Harvard Architecture. The ADSP-21267 is source code compatible with the ADSP-2136x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x .

ADSP-21261

ADSP-21262

ADSP-21266

ADSP-2100A

ADSP-2101

ADSP-21020

ADSP-2103

ADSP-2104

ADSP-2105

ADSP-21060

ADSP-21060C

ADSP-21060L

ADSP-21060LC